| CAUSE: | You used the Create/Update > Create HDL Design File for Current File command (File menu) to overwrite the target VHDL Design File (.vhd) or Verilog Design File (.v). However, the Quartus II software could not remove the existing VHDL or Verilog HDL Design File. This message can occur when the target design file is read-only or when you do not have permission to edit the design file. |
| ACTION: | Click OK to close the message dialog box, and then make sure the file is not read-only and that you have permission to edit the file and then create the new VHDL or Verilog Design File again. |
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