Quartus

Run timing analysis before generating netlist for the selected timing analysis tool

CAUSE: You directed the Compiler to generate an IBIS Output File (.ibs) for performing board-level signal integrity verification of Altera devices with other EDA tools, and then compiled the design. However, to generate an IBIS Output File, you must first run a timing analysis before the Quartus II software can generate the IBIS Output File.
ACTION: Click OK to close the message dialog box, and run a timing analysis.

See also:

Running a Timing Analysis
Specifying EDA Tool Settings

- PLDWorld -

 
Created by chm2web html help conversion utility.