| CAUSE: | You tried to generate output netlist files, such as VHDL Output Files (.vho) or Verilog Output Files (.vo) and their associated Standard Delay Format Output Files (.sdo), by using the EDA Tool Post-Compilation Commands > Write Output Netlists command (Processing menu), but the Quartus II software cannot generate the files because the project either has not been compiled, or did not compile successfully. |
| ACTION: | Click OK to close the message dialog box. If necessary, correct any unresolved compilation errors, and compile the project successfully. |
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- PLDWorld - |
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