Quartus

Can't generate Verilog Output File, VHDL Output File, or other output files for third party tools -- specify a simulation or timing analysis tool

CAUSE: You chose EDA Tool Post-Compilation Commands > Write Output Netlists, but did not specify any simulation or timing analysis tools for the current project. The Quartus II software is therefore unable to generate a Verilog Output File (.vo), VHDL Output File(.vho), or other output files for third party tools.
ACTION: Specify a simulation tool or timing analysis tool for the current project.

See also:

Specifying EDA Tool Settings

- PLDWorld -

 
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