You started generation of a Verilog Design File (.v). As a result, the Quartus II software has completed one of the following actions:

• Completed generation of a Verilog Design File from a Block Design File (.bdf) either successfully or unsuccessfully.

• Stopped generation of a Verilog Design File when you directed the Quartus II software to stop the process.

• Canceled generation of the Verilog Design File due to an error.

The message text indicates which action occurred.

Click OK to close the message dialog box, and then perform one of the following actions:

• If generation of the Verilog Design File was successful, no action is required.

• If generation of the Verilog Design File was unsuccessful, you can locate the sources of error and/or warning messages in the Messages window.

• If you stopped generation, you can restart generation of the Verilog Design File from the beginning.

• If the Quartus II software canceled generation due to an error, contact Altera Applications for assistance.