| CAUSE: | You specified a formal verification tool for the current project, and compiled the current design. However, the formal verification feature is not supported for the selected device. This feature is supported for only APEX 20KC, APEX 20KE, and APEX II devices. As a result, the Quartus II software will not create a Verilog Quartus Mapping File (.vqm) netlist or tool invocation script. |
| ACTION: | No action is required. If you want to use a formal verification tool, select a device family that supports this feature. |
See also:
Specifying EDA Tool Settings
Specifying the Device Family & Device for Compilation
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