| CAUSE: | You directed the Compiler to output a Excalibur embedded processor stripe as a single entity in a VHDL Output File (.vho) or as a single module in a Verilog Output File (.vo) for an ARM-based Excalibur design, and compiled the design. However, the Compiler cannot write out the stripe as a single module/entity in the netlist output because the Fitter did not place the dual-port RAM blocks. To place the dual-port RAM blocks, you must perform a full compilation. |
| ACTION: | Perform a full compilation on the design and write the stripe as a single module/entity in the netlist output. |
See also:
Compiling a Design
Specifying Verilog HDL Output Settings
Specifying VHDL Output Settings
|
- PLDWorld - |
|
|
| Created by chm2web html help conversion utility. |