| CAUSE: |
The memory width value you specified in a design file (Block Design File (.bdf), Text Design File (.tdf), VHDL Design File (.vhd), Verilog Design File (.v), or EDIF Input File (.edf)) of a design does not match the memory width value you specified in the Memory Initialization File (.mif). This condition occurs when you specify a memory width in the design file that his greater than the memory width defined in the MIF or HEX File. The Quartus II software is therefore setting the initial value for the remaining bits to 0. |
