| CAUSE: |
The memory depth value you specified in a design file (Block Design File (.bdf), Text Design File (.tdf), VHDL Design File (.vhd), Verilog Design File (.v), or EDIF Input File (.edf)) of a design does not match the specified memory depth value in the Memory Initialization File (.mif). This condition occurs when you specify a memory depth in the design file that is greater than the depth defined in the MIF or HEX File. The Quartus II software is therefore setting the initial value for the remaining addresses to never match. |
