| CAUSE: |
The memory depth value you specified in a design file (Block Design File (.bdf), Text Design File (.tdf), VHDL Design File (.vhd), Verilog Design File (.v), or EDIF Input File (.edf)) for a design does not match the memory depth value you specified in the Memory Initialization File (.mif). This condition occurs when you specify a memory depth in the design file that is less than the memory depth defined in the MIF or HEX File. The Quartus II software has therefore truncated the remaining initial content value to fit RAM. |
