Quartus

Board delay between clock output and feedback pins must be zero or greater -- assuming zero delay through board

CAUSE: You specified a negative board delay between the clock output and feedback pins of a ClockLock PLL. However, you must specify a number greater than zero between these pins.
ACTION: No action is required. The Compiler will assume a zero board delay.

- PLDWorld -

 
Created by chm2web html help conversion utility.