In the current design, the Design Assistant found the specified number of structures where you implemented asynchronous load signals. However, because one logic cell does not directly support the implementation of a signal in the design, the design requires more than one logic cell to implement the signal. The multiple logic cells may cause glitches and other problems in the design. The submessage(s) of this message list the asynchronous load structure(s) that the Design Assistant found.

This rule applies only to designs that the Logic Synthesizer has processed, but the Fitter has not processed, during a compilation.