In the current design, the Design Assistant found the specified number of nodes where a gated clock (which is combinatorial logic used as a clock signal) does not follow one or more of the following guidelines and therefore causes errors in the design:

• The gating logic should be a two-input AND gate or a two-input OR gate.

• There should be only one input pin that acts as a primary input clock signal to the AND or OR gate.

• The non-clock input clock enable signal to the AND or OR gate should be synchronized with a register. The register should be clocked by the same input pin that acts as the primary input clock signal to the AND or OR gate.

• If the gated clock uses an AND gate, the clock port of the register that drives the AND gate should be active on the falling edge and the clock port of the register driven by the AND gate should be active on the rising edge.

  or

  If the gated clock uses an OR gate, the clock port of the register that drives the OR gate should be active on the rising edge and the clock port of the register driven by the OR gate should be active on the falling edge.

The submessage(s) of this message list the node(s) that the Design Assistant found.