In the current design, the Design Assistant found the specified number of nodes where a gated reset (which is combinatorial logic used as a reset signal) is generated in one clock domain and used in one or more other, asynchronous clock domains. However, the synchronization of the gated reset does not follow the following guidelines and therefore causes metastability problems in the design:

• The gated reset should be synchronized with two or more cascading registers in the receiving asynchronous clock domain.

• The cascading registers should be triggered on the same clock edge.

• There should be no logic between the output of the transmitting clock domain and the cascaded registers in the receiving asynchronous clock domain.

The submessage(s) of this message list the node(s) that the Design Assistant found.