| CAUSE: | In the current design, the Design Assistant found the specified number of nodes where a gated reset (which is combinatorial logic used as a reset signal) is generated in one clock domain and used in one or more other, asynchronous clock domains. However, the gated reset is not synchronized. To reduce metastability problems, the gated reset should be synchronized with two or more cascading registers in the receiving asynchronous clock domain. The submessage(s) of this message list the node(s) that the Design Assistant found. |
| ACTION: | Synchronize the gated resets. |
See also:
Analyzing Designs with the Design Assistant
Gated Reset That is Generated in One Clock Domain and Used in Other, Asynchronous Clock Domains Should be Synchronized
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