| CAUSE: | You turned on Perform WYSIWYG primitive resynthesis, specified a formal verification tool for the current project, and compiled the design. However, formal verification may give mismatches between the pre- and post-Quartus II netlists if logic elements are modified in the design due to this option. |
| ACTION: | Turn off Perform WYSIWYG primitive resynthesis and recompile the design. |
See also:
Optimizing Netlists During Synthesis & Fitting
Specifying EDA Tool Settings
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