Quartus

Switched primary clock for PLL <name> because its clock input pin <name> assigned to I/O pin that does not feed primary clock input port of PLL

CAUSE: You assigned the specified clock input pin, clock0 or clock1, as the primary clock of the specified PLL, and you assigned the specified input clock to an I/O pin. However, the I/O pin can feed only the clock input port clock1 or clock0 of the specified PLL, which is not the primary clock input port. Therefore, the Fitter switched the primary clock for the specified PLL.
ACTION: Delete or change the location assignment for the specified clock input pin, or modify the design to change the primary clock for the PLL.

See also:

Assigning an Entity or Node to a Location
Changing Assignments
Deleting Assignments in the Assignment Organizer
Overview: Making Assignments
Overview: Working with Assignments in the Floorplan Editor

- PLDWorld -

 
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