Quartus

Design name for <name> contains a number -- illegal for Verilog HDL and VHDL -- adding "\\" in front of name

CAUSE: You used the Create HDL Design File for Current File command (Tools menu), but the current Block Design File (.bdf) or Graphic Design File (.gdf) design name contains a number. The design will not compile once it is converted to a Verilog Design File (.v) or a VHDL Design File (.vhd).
ACTION: No action is required. The Quartus II software changed the name by adding a "\" in front of the name. To avoid receiving this message in the future, name the BDF or GDF without numbers.

- PLDWorld -

 
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