| CAUSE: | You directed the Compiler to generate an IBIS Output File (.ibs) for performing board-level signal integrity verification of Altera devices with other EDA tools, specified that the minimum or maximum RLC (resistance, inductance, and capacitance) IBIS model values be used for the I/O, dedicated input, VCC, GND, and global clock pins in the IBIS Output File, and then compiled the project. However, minimum and maximum RLC values are not available for the currently selected device. Therefore, the Quartus II software is generating the IBIS Output File with typical RLC values. |
| ACTION: | If typical RLC values in the IBIS Output File are satisfactory, no action is required. Contact Altera Applications if you need minimum and maximum RLC values for this device. |
See also:
Specifying EDA Tool Settings
Specifying IBIS Output Settings
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