| CAUSE: | You directed the Compiler to generate an IBIS Output File (.ibs) for performing board-level signal integrity verification of Altera devices with other EDA tools, specified that the minimum or maximum RLC (resistance, inductance, and capacitance) IBIS model values be used for the I/O, dedicated input, VCC, GND, and global clock pins in the IBIS Output File, and then compiled the project. However, the appropriate IBIS model for the specified pin in the top-level design file, that corresponds to the specified pin in the device package, is not available. |
| ACTION: | For the latest IBIS models, go to the Quartus II IBIS File section of the Altera web site. Contact Altera Applications if you cannot find the appropriate IBIS model. |
See also:
Specifying EDA Tool Settings
Specifying IBIS Output Settings
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