CAUSE: | Output pins minimized to VCC or GND in a design file. This condition may be the result of optimizations performed during logic synthesis. |
ACTION: | If you intended the output pins to behave in this manner, no action is required. Otherwise, check the design file for errors and ensure that the project's logic does not reduce to VCC or GND . |
- PLDWorld - |
|
Created by chm2web html help conversion utility. |