| CAUSE: | You assigned the Virtual Pin logic option to one or more nodes in the current design. However, the current target device you specified for the design does not support virtual pins. When this condition occurs, the Compiler ignores the Virtual Pin assignment(s). The Virtual Pin logic option is only available for APEX 20K and Stratix device families. |
| ACTION: | No action is required. However, to avoid receiving this message in the future, remove the Virtual Pin assignment from the design, or target a device family that supports virtual pins. |
See also:
Changing Assignments
Overview: Making Assignments
Specifying the Device Family & Device for Compilation
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