| CAUSE 1: | You specified a logic level of X or Z for the write enable of the specified memory segment at the specified time in the vector source file, but the logic level must be 0 or 1. |
| ACTION: | Edit the vector source file to make sure the logic level of the write enable is 0 or 1. |
| CAUSE 2: | A setup or hold violation on the specified write enable register at the specified time is causing the output logic level of the register to be X or Z, but the logic level must be 0 or 1. |
| ACTION: | Correct the setup or hold violation by Editing the vector source file to make sure the logic level of the write enable register does not change so close to the clock. |
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