| CAUSE: | During simulation, the rx_deskew signal of the specified LVDS Receiver PLL was de-asserted at the specified time in the vector source file before calibration was complete. The rx_deskew signal must remain asserted at least three clock cycles for the Quartus II software to complete calibration. |
| ACTION: | Edit the vector source file so the rx_deskew signal stays asserted for at least three consecutive cycles with the valid calibration pattern. |
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