| CAUSE: | The specified ClockLock PLL lost the lock on its input signal at the specified time in the vector source file because the input signal feeding the ClockLock PLL did not maintain a 50% duty cycle. However, an input signal feeding a ClockLock PLL must maintain a 50% duty cycle. |
| ACTION: | Edit the vector source file so the input signal feeding the ClockLock PLL maintains a 50% duty cycle at the specified time. |
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- PLDWorld - |
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