| CAUSE: | The specified ClockLock PLL lost the lock on its input signal at the specified time in the vector source file because the frequency of the ClockLock PLL waveform does not match the frequency of the corresponding ClockLock PLL in the design file. |
| ACTION: | Overwrite the input waveform of the ClockLock PLL with a waveform of the same frequency specified in the design file. |
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