| CAUSE: | The specified ClockLock PLL lost the lock on its input signal at the specified time in the vector source file because the logic level of the input signal was other than 0 or 1. However, the input signal to the ClockLock PLL must have a logic level of 0 or 1. |
| ACTION: | Edit the vector source file so the input feeding the ClockLock PLL has a logic level of 0 or 1 at the specified time. |
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- PLDWorld - |
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