| CAUSE: | You specified external input and/or output delay assignments. However, the Quartus II software ignores these assignments unless you specify that the fMAX calculation in timing analysis should include external delays to and from device pins. The Quartus II software may still use these external input and/or output delay assignments to calculate the feedback delay of a PLL in external feedback mode, where appropriate. |
| ACTION: | Remove all external delay assignments, or specify that the fMAX calculation should include external delays to and from device pins. |
See also:
Creating Clock Settings
Editing Clock Settings
Overview: Using the Timing Analyzer
Specifying Project-Wide Timing Requirements
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