Quartus

Clock <name> frequency requirement of <number> overrides <name> PLL <name> input frequency requirement of <number>

CAUSE: You used the Clock Settings timing assignment to create clock settings that define the specified frequency requirement for the specified clock. However, the specified frequency requirement of the clock differs from the specified input frequency requirement of the specified PLL that it feeds. When this condition occurs in a Stratix design, the clock signal frequency requirement overrides the PLL input frequency requirement.
ACTION: No action is required.

See also:

Creating Clock Settings
Overview: Using the Timing Analyzer

- PLDWorld -

 
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