| CAUSE: | You used the Clock Settings logic option to create clock settings that define the specified frequency requirement for the specified clock. However, the frequency requirement of the clock differs from the specified input frequency requirement of the specified ClockLock PLL that it feeds. When this condition occurs, the ClockLock PLL input frequency requirement overrides the clock signal frequency requirement. Therefore, the Timing Analyzer reports the slack of the ClockLock PLL input frequency requirement in the Clock Requirement section of the Compilation Report. |
| ACTION: | Remove the unnecessary Clock Settings assigned to the clock signal feeding the ClockLock PLL. It is not necessary to assign clock settings to a clock signal that feeds a ClockLock PLL because the Quartus II software automatically creates appropriate clock settings for these signals, based on the ClockLock PLL specifications, during compilation. You can view the timing analysis results in the Report window |
See also:
Creating Clock Settings
Deleting Clock Settings
Overview: Using the Timing Analyzer
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