| CAUSE: |
The specified default required fMAX differs from the specified ClockLock PLL's input frequency requirement. The Quartus II software automatically creates and assigns appropriate Clock Settings, based on the specifications of the ClockLock PLL, to the ClockLock PLL during compilation. When the ClockLock PLL frequency requirement is different from the default required fMAX, the ClockLock PLL frequency requirement overrides the default required fMAX on that clock signal. Therefore, the Timing Analyzer reports the slack of the ClockLock PLL input frequency requirement in the Clock Requirement section of the Compilation Report. |
