| CAUSE: | The Timing Analyzer found a combinatorial loop of the specified number of nodes that exceeds the MAX_SCC_SIZE specified in the Project Settings File (.psf) for the current project. Large loops are usually the result of a design error. When this condition occurs, the Timing Analyzer only estimates the delay through the loop. |
| ACTION: | If this loop is intentional, you can change the number of nodes in a loop that the Timing Analyzer will analyze by specifying a value for the MAX_SCC_SIZE timing assignment in the Assignment Organizer. However, specifying a very high value for this assignment may result in extremely long analysis times. If this loop is unintentional, break the loop in the design. |
See also:
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- PLDWorld - |
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