Quartus

Verilog HDL or VHDL warning: <text>


CAUSE: Integrated Synthesis generated the specified warning for a Verilog Design File (.v) or VHDL Design File (.vhd).
ACTION: Edit the file to avoid problems in the future processing of the design, or to avoid receiving this message in the future. A future version of the Quartus II software will provide more detailed information about this warning.

- PLDWorld -

 

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