Quartus

Verilog HDL error at <location>: left index of part-select of variable <name> is out of address bounds -- returning don't care (X) value

CAUSE: In a Verilog Design File (.v) at the specified location, you used a part-select for the specified variable. However, the left index of this part-select is greater than the declared address range for the variable. The return value of the expression is being considered as don't care (X).
ACTION: Edit the design to make sure the part-select is within the declared address range for the variable.

See also:

Section 4 of the IEEE Std. 1364-2001 IEEE Standard Verilog Hardware Description Language manual

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