Quartus

Verilog HDL Case Statement error at <location>: ignoring Case Statements that contain X or Z value

CAUSE: In a Case Statement at the specified location in a Verilog Design File (.v), you used a don't care (X) or high impedance (Z) value. Case Statements that contain X or Z values are not supported by Integrated Synthesis and will be ignored.
ACTION: Edit the design to specify numeric values for Case Statements.

See also:

Section 9.5 of the IEEE Std. 1364-2001 IEEE Standard Verilog Hardware Description Language manual

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