| CAUSE: | In a Case Statement at the specified location in a Verilog Design File (.v), you specified a case item expression that has more significant bits than the number of bits in the case expression that it is being compared against. As a result, the case item expression can never apply, and is ignored by the Quartus II software. |
| ACTION: | No action is required. To avoid receiving this message in the future, remove bits from the case item expression until the bit length matches that of the case expression. |
See also:
Section 9.5 of the IEEE Std. 1364-2001 IEEE Standard Verilog Hardware Description Language manual
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