| CAUSE: | In a Block Statement at the specified location in a Verilog Design File (.v), you used a Disable Statement. However, although Disable Statements are supported in Verilog HDL, they are not supported in the Quartus II software. The Compiler is ignoring the Disable Statement. |
| ACTION: | No action is required. To avoid receiving this message in the future, use an If Statement to specify condition expressions that control the termination condition inside the Block Statement. |
See also:
Sections 9.6, 9.7, 9.8, and 11 of the IEEE Std. 1364-2001 IEEE Standard Verilog Hardware Description Language manual
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