Quartus

Verilog HDL User-Defined Primitive Declaration warning at <location>: user-defined primitive table is empty

CAUSE: In a User-Defined Primitive (UDP) Declaration at the specified location in a Verilog Design File (.v), you used a UDP table that is empty. As a result, Integrated Syntheses will create an empty primitive gate.
ACTION: No action is required. To avoid receiving this message in the future, enter the correct logic function information into the UDP table.

See also:

Section 8 of the IEEE Std. 1364-2001 IEEE Standard Verilog Hardware Description Language manual

- PLDWorld -

 
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