Quartus

Verilog HDL syntax warning at <location>: extra block comment delimiter characters (slash and asterisk) within block comment

CAUSE: In a Verilog Design File (.v) at the specified location, a line contains extra block comment delimiter characters (that is, a slash and an asterisk, or /*), within a /* */-style or block comment. Integrated Synthesis is ignoring the extra /* characters.
ACTION: No action is required. To avoid receiving this message in the future, check the comment text for extra /* characters and remove them.

See also:

Section 2.3 of the IEEE Std. 1364-2001 IEEE Standard Verilog Hardware Description Language manual

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