Quartus

Verilog HDL unsupported feature warning at <location>: bidirectional pass switch gate primitive <name> is not supported and will be implemented as wire

CAUSE: In a Verilog Design File (.v) at the specified location, you used the specified bidirectional pass switch gate primitive (tran or rtran). However, bidirectional pass switch gate primitives are not supported by the Quartus II software, so Integrated Synthesis will implement the primitive as a wire.
ACTION: No action required. To avoid receiving this message in the future, edit the design to replace an enabled bidirectional pass gate with two unidirectional enabled pass gates.

See also:

Section 7 of the IEEE Std. 1364-2001 IEEE Standard Verilog Hardware Description Language manual

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