| CAUSE: | In a Verilog Design File (.v) at the specified location, you used an Initial Construct to specify initial circuit conditions for simulation. Although Verilog HDL supports Initial Constructs, Integrated Synthesis does not support Initial Constructs, and will ignore the associated assignments. |
| ACTION: | No action is required. To avoid receiving this message in the future, check the circuit to make sure the undefined initial state will not cause a functional failure. If necessary, use a reset signal to put the circuit into the desired initial state. |
See also:
Sections 9.1 and 9.9 of the IEEE Std. 1364-2001 IEEE Standard Verilog Hardware Description Language manual
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