| CAUSE: | In a Verilog Design File (.v) at the specified location, you used a Task Enable Statement to enable a system task. The Quartus II software does not support using a Task Enable Statement to enable a system task. As a result, Integrated Synthesis is ignoring the Task Enable Statement. |
| ACTION: | No action is required. To avoid receiving this message in the future, you can remove the Task Enable Statement. |
See also:
Section 10.2 of the IEEE Std. 1364-2001 IEEE Standard Verilog Hardware Description Language manual
|
- PLDWorld - |
|
|
| Created by chm2web html help conversion utility. |