Quartus

Verilog HDL unsupported feature warning at <location>: system timing check ignored

CAUSE: In a Verilog Design File (.v) at the specified location, you used a system timing check. The Quartus II software does not support system timing checks, so any system timing checks you specify will be ignored.
ACTION: No action is required. To avoid receiving this message in the future, remove the system timing check.

See also:

Section 15 of the IEEE Std. 1364-2001 IEEE Standard Verilog Hardware Description Language manual

- PLDWorld -

 
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