| CAUSE: | In a Verilog Design File (.v) at the specified location, you specified a memory size; however, the memory size you specified is greater than or equal to 2**24 bits. Although the specified memory size is supported, it is very large. |
| ACTION: | No action is required. To avoid receiving this message in the future, reduce the memory size to less than 2**24 bits if it is appropriate for the design. |
See also:
Section 3.10.3 of the IEEE Std. 1364-2001 IEEE Standard Verilog Hardware Description Language manual
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