| CAUSE: | In a Verilog Design File (.v) at the specified location, you used the specified vector size, which greater than or equal to 2**16 bits. Although the specified vector size is legal, it is very large. |
| ACTION: | No action is required. To avoid receiving this message in the future, reduce the vector size to less than 2**16 bits if it is appropriate for the design. |
See also:
Sections 3.3 and 3.10 of the IEEE Std. 1364-2001 IEEE Standard Verilog Hardware Description Language manual
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