| CAUSE: | In a Verilog Design File (.v) at the specified location, you attempted to use the specified macro by typing the (`) character followed by the text macro name, but the macro has not been defined with a `define directive. This message may occur if you forgot to define the macro, or it may also occur if you were not intending to use a macro, but accidentally typed an accent grave or "back tick" character (`). |
| ACTION: | Define the macro, or if you were not intending to use a macro, remove the ` character. |
See also:
Section 19 of the IEEE Std. 1364-2001 IEEE Standard Verilog Hardware Description Language manual
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