| CAUSE: | In a Component Configuration at the specified location in a VHDL Design File (.vhd), you used a Binding Indication to bind the specified component to a design entity. However, you already bound the component to a design entity using a different Binding Indication. As a result, Integrated Synthesis ignored the second Binding Indication. |
| ACTION: | If Integrated Synthesis is using the wrong Binding Indication, or you want to avoid receiving this message in the future, remove one of the Binding Indications from the VHDL Design File. Otherwise, no action is required. |
See also:
Sections 1.3.2 and 5.2.1 of the IEEE Std 1076-1993 IEEE Standard VHDL Language Reference Manual
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