| CAUSE: | In a Component Configuration at the specified location in a VHDL Design File, you used the ALL keyword and a Binding Indication to bind all instances of a component to a design entity. However, you already bound the specified component to a design entity using a different Binding Indication. As a result, Integrated Synthesis ignored the second Binding Indication for the specified component. |
| ACTION: | If Integrated Synthesis is using the wrong Binding Indication, or you want to avoid receiving this message in the future, remove one of the Binding Indications from the VHDL Design File or change the ALL keyword to the OTHERS keyword for the Binding Indication. Otherwise, no action is required. |
See also:
Sections 1.3.2 and 5.2.1 of the IEEE Std 1076-1993 IEEE Standard VHDL Language Reference Manual
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