| CAUSE 1: | You used the Create/Update > Create Design File from Selected Block command (File menu) to generate a Verilog Design File (.v), VHDL Design File (.vhd), AHDL Text Design File (.tdf), or Block Design File (.bdf) for the selected block with the specified name, but a file with that name already exists for the project. The Quartus II software is asking if you would like to update the existing file from the selected block. |
| ACTION: | Click Yes to update the existing design file, click No to generate another design file with different name, or click Cancel to cancel the operation. |
| CAUSE 2: | You used the Create/Update > Update Design File from Selected Block command (File menu) to update the Verilog Design File, VHDL Design File, TDF, or BDF for the selected block with the specified name, but a file with that name already exists for the project. The Quartus II software is asking if you would like to update the existing file from the selected block. |
| ACTION: | Click Yes to update the specified design file, or click No or Cancel to cancel the operation. |
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