| CAUSE: | You used the Create/Update > Create HDL Design File for Current File command (File menu) to generate a VHDL Design File (.vhd) or Verilog Design File (.v) from the current Block Design File (.bdf). However, the Quartus II software cannot generate the file because it has the same name as an existing VHDL Design File or Verilog Design File. |
| ACTION: | Click Yes to close the message dialog box and overwrite the existing file, or click No and then delete or rename the existing design file, and create the new VHDL or Verilog Design File again. |
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